Performance analysis of a dual round robin matching switch with exhaustive service

Absbactvirtual Output Queuing is widely used by fixedlength high-speed switches to overcome head-of-line blocking. This is done by means of matching algorithms. M a x i " matching algorithms have good performance, hut their implementation complexity is quite high. Maximal matching algorith~ns need speedup to guarantee good performance. Iterative algorithms (such as PIM and ISLIP) use multiple iterations to converge on a maximal match. The Dual Round-Robm Matching (DRRM) scheme has performance similar to SLIP and lower impnementation complexity. The ohjective of matching algorithms is to reduce the matching overhead for each time slot. The EXbaus$ivi: Semce Dual Round-Robm Matching (EDRRM) algorithm amortizes the cost of a match over multiple time slots While EDRRlCI suf€ers from a thmughput below 100% for small switch sizes, it i n conjectured to achieve an asymptotic 100% throughput under uniform M e . Simulatious show that it achieves high thmnghpd under nonuniform traflie Its delay performance is not sensitive to traflic hurstiness, switch size and packet length. In an EDRRM switch cells helonging to the same packet are transferred to the output cont inu~ly , which leads to good packet delay performance and simplifies the implementation of packet reassembly. Io this paper we analyze the performance of an EDRRM switch by using an exhaustive service random poluog system model. This was used to predict the performance of switches t w large to he simulated within a rearonahle run time.